The reduction in the scale of integrated circuits requires the reduction of lithograph resolution limits. Generally speaking, the minimum pitch of integrated circuits cannot be less than the lithograph resolution limit. However, there are exceptions. By adopting certain techniques, it is possible to reduce the pitch of integrated circuits below the lithograph resolution limit, although such techniques typically require more process steps.
FIGS. 1 through 3 illustrate cross-sectional views of intermediate stages in a conventional process for achieving a below-lithograph-limitation pitch. Referring to FIG. 1, silicon substrate 10 is provided, which will be etched to form patterns, such as fins, in subsequent process steps. The formation of the fins requires the help of the overlying layers that are used for lithography purposes. The overlying layers include a first ashing removable dielectric (ARD) 12, silicon oxynitride 14, a second ARD 16, silicon oxynitride 18, and photo resist 20. Photo resist 20 is patterned.
Referring to FIG. 2, the patterns of photo resist 20 are transferred to the underlying silicon oxynitride 18 and second ARD 16 by dry etching. Typically, silicon oxynitride 18 will have remaining portions left over second ARD 16. Next, as shown in FIG. 3, spacer layer 22 is formed using plasma enhanced chemical vapor deposition (PECVD). In technical generations with large pitches, for example, greater than about 50 nm, spacer layer 22 is relatively conformal. However, for integrated circuits formed using 50 nm technology and below, the method is no longer usable. The reason is that PECVD is sensitive to surface conditions. The resulting spacer layer 22 is thus highly non-conformal, and for below 50 nm technologies, such non-conformity becomes too significant. It was noted that the thickness of the cap portions of spacer layer 22 is significantly greater than the thickness of the sidewall portions of spacer layer 22 on the sidewalls of second ARD 16. In subsequent steps, second ARD 16 needs to be removed from between the sidewall portions of spacer layer 22. Therefore, the increased thickness of the cap portions of spacer layer 22 adversely affects the subsequent process steps.
On the other hand, deposition methods for forming conformal films, such as atomic layer deposition (ALD), cannot be used to solve the above-discussed problem. It has been found that when ALD is used to form spacer layer 22, second ARD 16 as shown in FIG. 2 peels off. New methods are thus needed to solve the above-discussed problems.